1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
The scaling down of the semiconductor manufacturing process is an effective technique for an LSI to improve its performance. However, the scaling down of the manufacturing process has lead to an increase in variations among transistors, which makes it difficult to maintain the yield of LSI. Particularly, because SRAM (Static Random Access Memory), which is one of semiconductor memory devices, uses fine transistors, the effect of variations is significant. It is thus increasingly important to solve the issue of a decrease in yield in SRAM.
Memory cells (SRAM cells) and sense amplifiers are component elements of SRAM. If variation occurs in the SRAM cells, a read margin or a write margin of the SRAM cell is reduced. This causes read-data destruction or a write failure.
On the other hand, if variation occurs in the sense amplifier, an input offset voltage appears in the sense amplifier. The input offset voltage means an insensitive zone of an input voltage that occurs due to the left-to-right mismatch of the sense amplifier caused by variation. In order to make right determination about the data read from the SRAM cell, it is necessary that the bit line voltage difference exceeds the offset voltage in the sense amplifier at the time of activating the sense amplifier.
FIG. 38 shows a configuration of a typical SRAM 1. The SRAM 1 includes a memory cell array 10, a plurality of precharge circuits 20, a column selector 30, and a sense amplifier circuit 40.
In the memory cell array 10, a plurality of SRAM cells CELL are arranged in matrix. The SRAM cells are connected horizontally by word lines WL0 to WLm−1 and vertically by bit line pairs BL0 and BLB0 to BLn−1 and BLB1n−1. If one of the word lines is selected, cell currents flow from the SRAM cells connected to the selected word line. Consequently, each one of the bit line pairs connected to the SRAM cell is discharged. Then, the potentials of the relevant bit lines drop gradually from the precharge potential. The voltage difference thereby appears in the respective bit line pairs.
Next, one bit of n-bit column selection signal YS[n−1:0] is selected. Consequently, one pair of the bit line pairs BL0 and BLB0 to BLn−1 and BLB1n−1 is selected. The selected bit line pair and the sense amplifier circuit 40 are connected through the column selector 30. The bit-line voltage difference increases with time due to discharge by the cell current. After the bit-line voltage difference increases and exceeds the offset voltage of the sense amplifier circuit 40, the sense amplifier circuit 40 is activated. Consequently, read data OUT and OUTB appear in the sense amplifier outputs. Note that the time required from the word-line activation to the bit-line voltage difference exceeding the offset voltage of the sense amplifier circuit 40 is called bit line delay.
The longer bit line delay is required as the offset voltage of the sense amplifier circuit becomes larger due to an increase in variations caused by the scaling down of the manufacturing process. The bit line delay is dominant in operation delays of SRAM. Therefore, an increase in the bit line delay leads to degradation of the operating speed of SRAM. In order to avoid the degradation of the operating speed, it is needed to decrease the effect of the offset voltage in the sense amplifier circuit.
A sense amplifier circuit with circuit configuration including an offset voltage compensation mechanism that decreases an input offset voltage (which is referred to hereinafter as an offset voltage compensation sense amplifier) is disclosed in Japanese Unexamined Patent Application Publication No. 7-302497. The offset voltage compensation sense amplifier disclosed therein decreases the offset voltage by providing negative feedback to a fully differential amplifier and charging capacitors connected to input terminals.
Further, the similar offset voltage compensation sense amplifier is disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No 11-509667. The offset voltage compensation sense amplifier disclosed therein decreases the offset voltage by providing negative feedback to a differential amplifier using a cascode connection and charging capacitors connected to output terminals.